The present disclosure relates to non-volatile semiconductor memory devices, and more particularly to techniques reducing circuit areas.
In recent years, mobile phones (including smart phones), portable music players, digital cameras, and tablet terminals have been particularly increasingly demanded as electronic devices. Accordingly, non-volatile semiconductor memory devices have also been increasingly demanded, and techniques have been actively developed to increase the capacity, reduce the sizes, and perform high-speed rewrite, high-speed reading, and operation with low power consumption.
At present, flash memories are major non-volatile memories. In flash memories, data is rewritten in a microsecond or millisecond order, and a voltage of 10 V or more is needed to rewrite data. This often hinders an improvement in the performance of setting devices mounting flash memories.
In recent years, new non-volatile memories have been actively developed, which rewrite data at high speed with low power consumption as compared to the flash memories. For example, there are variable resistance memories (e.g., resistive random access memory (ReRAM)) using variable resistance elements as memory elements. In the variable resistance memories, data is rewritten in a nanosecond order, and a voltage of about 1.8 V is needed to rewrite data, thereby increasing the speed and reducing the power consumption as compared to the flash memories.
Japanese Unexamined Patent Publication No. 2004-234707 shows a circuit configuration of a ReRAM. Each memory cell of the ReRAM is formed by coupling a variable resistance element and a cell transistor in series. The ReRAM sets the resistances of the variable resistance elements to be low or high, for example, within the range from 1 KΩ to 1 MΩ, thereby storing “0” data or “1” data, respectively.
Where the variable resistance element is in the low resistance state, a large memory cell current flows. Where the variable resistance element is in the high resistance state, a small memory cell current flows. This change in the memory cell current according to the state of the variable resistance element is utilized, that is, the difference in the memory cell current is detected using a sense amplifier circuit, thereby reading data stored in a memory cell.
A reference cell is used to generate a reference current to determine the difference in the memory cell current using the sense amplifier circuit. The sense amplifier circuit compares the memory cell current to the reference current to identify the data stored in the memory cell. The reference cell formed by coupling a fixed resistance element, which is, for example, a polysilicon resistive element, to a cell transistor in series. See, for example, Wataru Otsuka, et al., A 4 Mb Conductive-Bridge Resistive Memory with 2.3 GB/s Read-Throughput and 216 MB/s Program Throughput, 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers, April 2011, pp 210-211. The resistance of the fixed resistance element is set to the medium value between the low resistance and the high resistance of the variable resistance element of the memory cell. Then, the reference current value in read operation is the medium value of the memory cell current value indicating “0” data and “1” data. As a result, the sense amplifier circuit identifies the data stored in the memory cell.
In ReRAMs, various types of reference currents are generated in read operation. For example, various types of currents such as normal reading reference currents, program verification reference currents used for verification reading in rewriting, and erase verification reference currents are generated as reading reference currents. In some cases, various types of reference currents are additionally generated to correct variations in reference currents for normal reading, program verification, and erase verification, depending on chips.
For example, in Japanese Unexamined Patent Publication No. 2004-234707, FIG. 4 shows a reference cell including four circuits, each of which is formed by coupling a fixed resistance element and a cell transistor in series. Different reference currents are generated depending on which cell transistor is selected. That is, a necessary reference current is generated by selecting a desired cell transistor in accordance with the normal reading, the program verification, or the erase verification.